1. Field of the Invention
The present invention generally relates to reduced power operation of digital circuitry and more specifically to a method and apparatus for operating logic circuitry with alternating power phases.
2. Description of the Related Art
Advances in VLSI fabrication in recent years have greatly increased the levels of integration in digital integrated circuitry with the advent of submicron geometries. However, there has also been an increase in the speed and functionality in such circuitry. One example is the Pentium III microprocessor, which has several million transistors in a 1 cm2 area. While these trends are good from the standpoint of delivering increased capabilities to the electronics consumer there has developed a major problem, which is the power consumption of these devices. The Pentium III processor, while having exceptional performance, also has exceptional power dissipation—in the range of about 27 watts for an 866 MHz Pentium III. Adding to the problem, many portable computer systems, such as laptops, personal organizers and cellular telephones, demand the use of the highest performance integrated circuitry but do not have the battery power to run such circuitry for extended periods of time. Battery systems simply have not kept pace with the demands of the technology. To make matters worse, many portable or mobile systems have physical size constraints that preclude the use of extensive cooling devices to remove the power from the integrated circuitry.
Most of the digital integrated circuitry used for today's high performance and high power devices is CMOS circuitry. Power consumption for CMOS circuitry is the sum of static power dissipation and dynamic power dissipation. The former PS is the result of leakage current while the latter PD is the sum of transient power consumption PT and capacitive-load power consumption PL.
Transient power consumption PT, in turn, results from current that travels between the supply and ground (known as through current) when the CMOS device switches and current required to charge internal switching nodes within the device (known as switching current), the charging and discharging of internal nodes being the predominant cause. Capacitive-load power consumption PL is caused by charging and discharging an external load capacitance.
FIG. 1 shows a typical CMOS inverter circuit 10 which includes a p-channel MOS transistor 12 and an n-channel MOS transistor 14, the gates 16, 18 of the transistors 12, 14 being connected together and to the inverter input 20, the drains 22, 24 of the transistors being connected together and to the inverter output 26. The source 30 of the p-channel transistor 12 is connected to the voltage supply Vdd and the source 28 of the n-channel transistor 14 is connected to ground (Vss). The output of the inverter 26 is connected to other CMOS circuitry whose loading characteristics are capacitive in nature. This external capacitive loading is modeled by a capacitor 32 connected to the inverter output 26. When the input 20 to the logic circuit 10 is driven low, p-channel transistor 12 turns on, causing the capacitive load 32 with value CL to be charged from the supply Vdd through the p-channel transistor 12 and registering a logic ONE at the output 26. Similarly, when the input 20 is driven high, the p-channel transistor 12 turns off and the n-channel transistor 14 turns on, allowing charge stored in the capacitive load 32 to be transferred through the n-channel transistor 14 to ground, thus registering a logic ZERO at the output 26. Each cycle of the input signal results in a transfer of charge to and from the capacitive load, which is equivalent to an energy transfer of (½×CL×ΔVC2) to charge and (½×CL×ΔVd2) to discharge the capacitive load, where CL is the value of the capacitive load, ΔVc, is the change in voltage across the capacitive load when charging the load and ΔVd, is change in voltage across the capacitive load when discharging the load. This energy ½×CL×(ΔVc2+ΔVd2) is dissipated as heat. Ultimately, the dynamic energy, on the order of 10−12 Joules (assuming CL to be about 1 pf, which includes load and wiring capacitance, and ΔV to be about a volt), used to operate the circuit of FIG. 1 over a single cycle is lost.
Furthermore, if the cycle of charging and discharging occurs at a frequency f, then the power consumed by the circuit of FIG. 1 is approximately f×C×(ΔV)2 where equal voltage changes are assumed for charging and discharging. Currently, the frequency of operation of CMOS circuits is as high as 109 Hz. This means that even though the energy consumed over one cycle by a simple CMOS gate is very low, the power consumed when a gate is operated continuously at very high frequencies can be appreciable (on the order of 10−3 Watts). When there are millions of such gates on a semiconductor die the problem is again multiplied resulting in many tens of Watts being consumed and a large fraction of that power being dissipated as heat.
A common approach to alleviate this problem has been to reduce the supply voltage because the savings in power consumption is proportional to the square of the voltage reduction. However, reduction of the power supply voltage causes other problems which include increasing the susceptibility of the circuit to noise and increased transistor leakage current because the threshold voltage of the MOS transistors must be reduced to permit the devices to operate on the lower supply voltage.
Therefore, there is a need for high-speed, high-functionality integrated circuit devices that have very low power consumption without depending on low supply voltages to achieve the reduction in power consumption.